1. Field of the Invention
The present invention relates to a semiconductor memory device including a plurality of memory arrays. More particularly, the present invention relates to a hierarchical bit line architecture in which a plurality of sub-bit lines are connected to one main bit line.
2. Description of the Background Art
Various types of semiconductor memory devices, such as DRAMs (dynamic random access memories), SRAMs (static random access memories) and ROMs (read-only memories), are used in various applications, but they share some common internal configurations. Main components of a semiconductor memory device include a memory array portion being a storage portion including a plurality of memory cells arranged in a regular pattern, and a peripheral portion provided around the memory array portion and including control circuits such as a row decoder and an amplifier.
One factor that dictates the overall performance of a semiconductor memory device is its memory capacity (the number of memory cells), and it is an object of research and development to make as many memory cells as possible per unit area. Generally, there are two possible approaches to this object. One is to reduce the size of a memory cell itself, and the other is to reduce the size of a non-memory cell portion such as a peripheral circuit.
The memory cell size has been reduced to the limit by using state-of-the-art processes and custom-designed mask patterns. The size of the non-memory cell portion has also been reduced by reducing the circuits, for example. With state-of-the-art processes, the area of the memory cell portion has been reduced to the limit, resulting in a side effect being an influence from neighboring patterns such as the loading effect. Therefore, it is necessary to give some considerations not only for memory cells themselves but also for neighboring patterns.
In a memory array including a plurality of memory cells arranged in a matrix pattern, a central memory cell located in a central portion of the memory array is surrounded by memory cells of the same shape. Therefore, there is a uniform influence of, for example, pattern reflections from surrounding cells during lithography, thus enabling a stable formation of patterns. However, a peripheral memory cell located in a peripheral portion of a memory array is surrounded by memory cell patterns and other circuits. Since the layout pattern of a memory cell is different from those of other circuits, peripheral memory cells are subject to non-uniform influence from the surroundings. Therefore, the resulting pattern of a peripheral memory cell will be different from that of a central memory cell, thus resulting in variations between these memory cells in terms of memory cell transistor characteristics such as the transistor size and the threshold value. The performance of a semiconductor memory device is very much dependent on the memory cell characteristics, and variations among memory cells directly affect the performance of the semiconductor memory device. Depending on the amount of variations, the performance of the semiconductor memory device is deteriorated significantly. In view of this, dummy patterns having the same shape as memory cells are provided in the memory array peripheral portion for stabilizing the pattern formation.
U.S. Pat. No. 5,267,208 discloses an example of a memory (SRAM), which is divided into sections by wiring regions, thereby resulting in non-uniform patterns, wherein a dummy pattern is provided in the non-uniform portion (under the wiring region).